1. Field of the Invention
The present invention relates to metal interconnections in semiconductor devices. More specifically, the present invention relates to metal interconnections for bit lines having low resistance, and a method of forming the same. The present invention encompasses techniques for reducing resistance of bit lines and for providing advanced morphology of metal interconnections associated with bit lines.
2. Description of the Related Art
Conventionally, increased integration density of semiconductor devices causes the number of fabricating steps to increase and design rules to become more restricted and complicated. Design rules in manufacturing semiconductor devices, e.g., semiconductor memories, are most relevant to a width of conductive lines for interconnecting between active regions, such as bit lines, word lines, and metal lines, or to operable pitches between the conductive interconnection lines. While narrower widths (or dimensions) of interconnection lines are helpful to enhance integration density of semiconductor memory devices, increased resistance thereon may affect propagation efficiencies of electrical carriers such as voltage or current. Such an increase of resistance through interconnection lines degrades operating speeds in semiconductor memory devices. This is especially problematic, as most semiconductor memory devices need to be operable in a higher frequency.
Procedures for forming typical interconnection lines, or bit lines, in a semiconductor memory device as shown in FIG. 1, are shown in FIGS. 2A through 2F and FIGS. 3A through 3F. FIGS. 2A through 2F illustrate procedures to complete bit lines in a view taken along sectional line X1-X1xe2x80x2 of FIG. 1. FIGS. 3A through 3F also illustrate these procedures in a view taken along sectional line X2-X2xe2x80x2 of FIG. 1, which is orthogonal to X1-X1xe2x80x2, both of FIG. 1.
Referring to FIGS. 2A and 3A, a contact hole 12 for a polysilicon plug is formed by a photolithography process after evaporating a first inter-layer insulation film 11 on a substrate 10. After depositing a polysilicon film on the first inter-layer insulation film 11 and the contact hole 12, a polysilicon plug 13 is patterned by a photolithography process. Next, a second interlayer insulation film 14 is deposited on the first inter-layer insulation film 11 and the polysilicon plug 13. A photolithography process is conducted to expose the polysilicon plug 13 by removing a portion of the second interlayer insulation film 14 on the polysilicon plug 13, so that a bit line contact hole (DC: direct contact) 15 is formed. The bit line contact hole 15 may also be seen in a top elevation view as reference numeral 100 in FIG. 1.
Referring to FIGS. 2B and 3B, a barrier metal 16 and a metal film 17 are sequentially deposited on the second inter-layer insulation film 14 and the bit line contact hole 15. The barrier metal 16 is made of Ti/TiN film evaporated by CVD (chemical vapor deposition). The metal film 17 is made of tungsten (W) evaporated by CVD.
Referring to FIGS. 2C and 3C, a CMP (chemical-mechanical polishing) is carried out to etch the barrier metal 16 and the metal film 17 flat. After the CMP process, the barrier metal 16 and the metal film 17 remain only in the bit line contact hole 15, forming a bit line plug 18. The CMP process removes other portions of the barrier metal 16 and the metal film 17 on the second inter-layer insulation film 14.
Referring to FIGS. 2D and 3D, a bit line metal film 19 is formed on the bit line plug 18 and the second inter-layer insulation film 14. The bit line metal film 19 is a tungsten film evaporated by CVD, so that the bit line plug 18 is defined to fill the contact hole 15.
Referring to FIGS. 2E and 3E, a capping layer 20 is deposited on the bit line metal film 19. The capping layer 20, made of a nitride, is utilized as a hard mask for a bit line patterning process performed in a subsequent step.
Finally, referring to FIGS. 2F and 3F, a photolithography process is used to pattern a bit line 21 (corresponding to reference numeral 110 shown in FIG. 1) formed from the bit line metal film 19 and the capping layer 20.
However, in the procedure of forming the bit line 21 according to the processing steps shown in FIGS. 2A-2F (or 3A-3F), there is a problem in that an over-etching occurs, which results in the removal of a portion of the CVD tungsten metal film 17 used for the plug 18 as shown in FIG. 2F. The over-etching after bit line patterning arises from the fact that a width of the bit line 110 of FIG. 1 (or 21 of FIGS. 2F and 3F) is intentionally defined to be narrower than a diameter of the contact hole 100 of FIG. 1 (or 15 of FIGS. 2F and 3F) because the bit line becomes more slender according to an increase in an integration density. The undesirable over-etch of the plug metal film 17 causes a single-bit fail that degrades reliability of a memory device and may cause subsequent processing difficulties.
To overcome these difficulties, a method has been suggested that uses a barrier metal formed on the plug metal film (i.e., the CVD tungsten film) as an etch stopper to protect the plug metal film against over-etching. FIGS. 4A-4F and 5A-5F illustrate steps in a conventional procedure that uses the barrier metal for protecting the plug metal film against over-etching. FIGS. 4A-4F illustrate processing steps and are shown taken along the sectional line X1-X1xe2x80x2 of FIG. 1. FIGS. 5A-5F illustrate the same processing steps and are shown taken along the sectional line X2-X2xe2x80x2 of FIG. 1.
Referring to FIGS. 4A and 5A, a contact hole 32 for a polysilicon plug is formed by a photolithography process after evaporating a first inter-layer insulation film 31 on a substrate 30. After depositing a polysilicon film on the first inter-layer insulation film 31 and the contact hole 32, a polysilicon plug 33 is patterned by a photolithography process. Next, a second interlayer insulation film 34 is deposited on the first inter-layer insulation film 31 and the polysilicon plug 33. A photolithography process is performed to expose the polysilicon plug 33 by removing a portion of the second interlayer insulation film 34 on the polysilicon plug 33, so that a bit line contact hole (DC: direct contact) 35 is formed. The bit line contact hole 35 may also be seen in a top elevation view as reference numeral 100 in FIG. 1.
Referring to FIGS. 4B and 5B, a barrier metal 36 and a metal film 37 are sequentially deposited on the second inter-layer insulation film 34 and the bit line contact hole 35. The barrier metal 36 is made of Ti/TiN film evaporated by CVD (chemical vapor deposition). The metal film 37 is tungsten (W) evaporated by CVD.
Referring to FIGS. 4C and 5C, a CMP (chemical-mechanical polishing) process is carried out to etch the barrier metal 36 and the metal film 37 flat. After the CMP process, the barrier metal 36 and the metal film 37 remain only in the bit line contact hole 35, forming a bit line plug 38. The CMP process removes other parts of the barrier metal 36 and the metal film 37 on the second inter-layer insulation film 34, so that the bit line plug 38 is defined to fill the contact hole 35.
Referring to FIGS. 4D and 5D, an additional barrier metal 39 is formed on the bit line plug 38 and the second inter-layer insulation film 34. The barrier metal 39 is a titanium nitride evaporated by CVD. The barrier metal 39 acts as an etch stopper in a subsequent processing step of patterning bit lines.
Referring to FIGS. 4E and 5E, a bit line metal film 40 and a bit line capping layer 41 are sequentially deposited on the barrier metal 39. The capping layer 41, made of a nitride, is utilized as a hard mask for a bit line patterning process performed in a subsequent step. The bit line metal film 40 is a tungsten film evaporated by CVD.
Finally, referring to FIGS. 4F and 5F, a photolithography process patterns a bit line 42 (corresponding to reference numeral 110 shown in FIG. 1), formed of the barrier metal 39, the bit line metal film 40, and the capping layer 41, by etching the capping layer 41, the bit line metal film 40, and the barrier metal in that order. At this time, the barrier metal 39 acts as an etch stopper when the capping layer 41 and the bit line metal film 40 are partially etched away.
The barrier metal 39, acting as an etch stopper, protects the metal film 37 from the etching process by which the bit line metal film 40 of CVD tungsten is removed, thereby enhancing operational reliabilities directed to the single-bit fail and facilitating performance of subsequent processing steps. Nevertheless, several defects also occur due to the presence of the barrier metal 39 under the bit line metal film 40 of CVD tungsten. These defects include an increased resistance of the bit lines and bad morphology.
FIG. 11A shows an example morphology, i.e., optical microscopy of a tungsten film as the bit line metal film that is evaporated on the barrier metal 39 of titanium nitride by means of CVD with a thickness of 800 xc3x85. As shown in FIG. 11A, resistance of the bit line, Rs, is 2.5 xcexa9, which is regarded to be more than any value normally acceptable, and morphology thereof rates at about 3.0 nm in the dimension of AFM RMS (Auto Force Microscopy Root Mean Square).
Therefore, with respect to the case that a bit line constructed of an 800 xc3x85 CVD tungsten film and a 2500 xc3x85 nitride film is formed on a CVD titanium nitride that acts as a barrier metal, an increased resistance of the bit line due to the barrier metal limits ACI CD (After Cleaning Inspection Critical Dimension) to be finer than 105 nm. Furthermore, such weak morphology (about 3.0 nm) is not helpful for reducing defects appearing after patterning bit lines, which causes limitations in decreasing width of bit lines.
It is therefore a feature of an embodiment of the present invention to provide a metal interconnection structure capable of high integration of a semiconductor device, and a method of forming the same.
It is another feature of an embodiment of the present invention to provide a metal interconnection structure that is capable of reducing resistance of bit lines even though a width of the bit lines becomes narrower, and a method of forming the same.
It is another feature of an embodiment of the present invention to provide a metal interconnection structure that is capable of obtaining better morphology for bit lines and a method of forming the same.
It is still another feature of an embodiment of the present invention to provide a metal interconnection structure that is capable of enhancing reliability of a semiconductor device and a method of forming the same.
It is yet another feature of an embodiment of the present invention to provide a metal interconnection structure having better morphology and lower resistance, for bit lines, and a method of forming the same.
In order to provide these and other features, according to an embodiment of the present invention, there is provided a method of forming an inter-layer insulation film on a semiconductor substrate, the inter-layer insulation film containing a bit line contact hole, forming a plug in the bit line contact hole, and forming a bit line including a bit line barrier metal formed on the plug and a bit line metal film formed on the bit line barrier metal and the inter-layer insulation film.
Preferably, the plug is formed by depositing a plug barrier metal on the inter-layer insulation film and in the bit line contact hole; depositing a plug metal film on the plug barrier metal; and forming the plug constructed of the plug barrier metal and the plug metal film, which fill the bit line contact hole, by etching the plug barrier metal and the plug metal film. The plug barrier metal is preferably made of a Ti/TiN film evaporated by means of a CVD process. The plug metal film is preferably made of a tungsten film evaporated by means of a CVD process. Preferably, the plug barrier metal and the plug metal film are etched flat by means of a CMP process or an etch-back process, so that they form the plug filling the bit line contact hole.
Several ways to form the bit line barrier metal will now be described. First, the bit line barrier metal is formed by partially etching the plug within the bit line contact hole; depositing the bit line barrier metal on the inter-layer insulation film and on the plug that is partially etched away; and etching the bit line barrier metal to be defined on the plug within the bit line contact hole. Alternatively, the bit line barrier metal may be formed by depositing a bit line barrier metal on the inter-layer insulation film and on the plug; and patterning the bit line barrier metal to be defined on the plug.
The bit line barrier metal is preferably a TiN film evaporated by means of either a CVD process or a sputtering process. The bit line metal film is preferably made of a sputtered tungsten film. The bit line further includes a capping layer made of a nitride film formed on the bit line metal film. A width of the bit line is smaller than a diameter of the contact hole.
Preferably, an embodiment of the present invention also provides a method of forming a metal interconnection structure including forming an inter-layer insulation film on a semiconductor substrate, the inter-layer insulation film containing a bit line contact hole; forming a plug in the bit line contact hole; partially etching the plug in the bit line contact hole; forming a bit line barrier metal completely on the plug that has been partially etched; and forming a bit line on the bit line barrier metal and the inter-layer insulation film.
Furthermore, an embodiment of the present invention also preferably provides a method of forming a metal interconnection structure including forming an inter-layer insulation film on a semiconductor substrate; forming a bit line contact hole by selectively etching the inter-layer insulation film; forming a plug in the bit line contact hole; depositing a bit line barrier metal on the plug and the inter-layer insulation film; etching the bit line barrier metal to be formed completely on the plug; and forming a bit line on the bit line barrier metal and the inter-layer insulation film.
In addition, an embodiment of the present invention provides an advanced structure of metal interconnection for a semiconductor device, including an inter-layer insulation film formed on a semiconductor substrate, containing a bit line contact hole, a plug formed in the contact hole, and a bit line including a bit line barrier metal defined on the plug within the contact hole, and a bit line metal film formed on the bit line barrier metal and the inter-layer insulation film.
The plug preferably includes a plug barrier metal formed in the contact hole, and a plug metal film formed on the plug barrier metal and partially filling the contact hole. The bit line barrier metal is preferably a TiN film formed on the plug metal film and filling the contact hole. The plug within the contact hole includes a plug barrier metal formed in the contact hole, and a plug metal film formed on the plug barrier metal and filling the contact hole. The bit line barrier metal is formed completely on the plug defined within the contact hole.
Another feature of an embodiment of the present invention referring to a metal interconnection structure of a semiconductor device includes an inter-layer insulation film formed on a semiconductor substrate containing a bit line contact hole; a plug partially filling the contact hole, a bit line barrier metal defined on the plug and filling the rest of the contact hole; and a bit line formed on the bit line barrier metal and the inter-layer insulation film.
Still another feature of an embodiment of the present invention referring to a metal interconnection structure of a semiconductor device includes an inter-layer insulation film formed on a semiconductor substrate containing a bit line contact hole; a plug completely filling the contact hole; a bit line barrier metal defined on the plug in the contact hole; and a bit line formed on the bit line barrier metal and the inter-layer insulation film.
These and other features and aspects of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.